1. Field of the Invention
The present invention generally relates to electronic circuitry. More particularly, the present invention relates to buffers.
2. Background Art
Buffer circuits typically are used to drive a low impedance while providing a high input impedance. For example, buffer circuits may be used at the interface of continuous-time and discrete-time circuits such as switched-capacitor sampling circuits to avoid the effects caused by sampling of the preceding continuous-time signal. Accordingly, buffer circuits are commonly used at the input of switched-capacitor based analog-to-digital converters (ADCs) such as sigma-delta ADCs, pipeline ADCs, algorithmic ADCs, etc.
A source-follower transistor is conventionally used as a buffer. In their simplest forms, source-follower transistor based buffers do not often meet the high linearity characteristics desired for many buffer circuit applications. In addition, charge glitches caused by a sampling circuit that follows a buffer circuit are typically coupled to the buffer circuit's input terminal through a parasitic capacitance “Cgs” of the source-follower transistor. This coupling can degrade the linearity of preceding continuous-time signals at the buffer circuit input. Accordingly, there is a need for a buffer circuit having high linearity.
Furthermore, buffer circuits, such as ones based on source-follower transistors, often generate an output signal having a level that is offset from the level of the corresponding buffer circuit input signal. It is often desirable to control the level of buffer output signals.
In addition, the level of a buffer circuit input signal may affect buffer circuit performance. Therefore, it is also often desirable to control the level of buffer input signals.